1. FIELD OF THE INVENTION
This invention relates to a chip carrier for semiconductor chips, more specifically, to a power, ground and decoupling lead structure whereby a minimum number of chip carrier leads are utilized for power and ground connection and whereby the lead structure provides an integral decoupling capacitor structure having substantially zero inductance.
2. DESCRIPTION OF THE PRIOR ART
Chip carriers for integrated circuit chips are well known in the art and are widely used. Such chip carriers have lead arrays thereon which extend from the outer edges of the chip carrier to a central portion of the carrier where they are then connected to bonding pads on semiconductor chips bonded at and to the center of the chip carrier. The leads on the chip carrier, by virtue of the need of high density, are very narrow and therefore have a recognizable electrical resistance. The chip mounted in the center of the chip carrier, during the time of arrival of a clock pulse, may switch a large number of transistors simultaneously, therefore providing an instantaneous high drain from the power supply. If the resistance of the conductors is sufficiently high, this results in a voltage drop across the chip which renders it sensitive to noise and can cause errors in switching. Therefore it is important to maintain substantially constant potential across the chip. Usually, an attempt is made to handle this problem by placing decoupling capacitors directly adjacent to the chip carrier. This serves to eliminate the problem of voltage drop in the voltage and ground plane in the circuit board or chip carrier but not inside the chip carrier itself. These instantaneous switchings create two types of problems, one is instantaneous voltage drop as noted above and the second is that the self-inductance in the switching network creates an inductive spike. This spike is a source of electrical noise. If a capacitor was available immediately adjacent to the chip with the capability of having zero measurable inductance, it would remove the spike and reduce the noise in the chip.